1. Field of the Invention
The present invention relates generally to semiconductor memory devices and, more particularly, to an improved semiconductor memory device with an increased capacitance of a capacitor. The invention further relates to a method of manufacturing such an improved semiconductor memory device.
2. Description of the Background Art
An IC memory often comprises a memory cell array including a number of storage elements, and a peripheral circuit required for inputting and outputting, which are formed on the same substrate.
FIG. 4 is a block diagram of one example of a general configuration of a random access memory (RAM). Referring to the figure, a plurality of word lines and bit lines are provided intersecting each other on a memory cell array 1. Memory cells are each provided at the intersections of the word lines and bit lines. Each of the memory cells is selected based on the intersection between one of the word lines selected by an X address buffer decoder 2 and one of the bit lines selected by a Y address buffer decoder 3. Data is written in a selected memory cell, or data stored in the selected memory cell is read out. An instruction of this data writing/reading is carried out by a read/write control signal (R/W) to be applied from an R/W control circuit 4. In data writing, input data (Din) is inputted to the selected memory cell via the R/W control circuit 4. In data reading, after detection by a sense amplifier 5, the data stored in the selected memory cell is amplified and then outputted as output data (Dout) via a data output buffer 6.
FIG. 5 is an equivalent circuit diagram of a dynamic memory cell shown for a description of the writing/reading operation of a memory cell.
Referring to the figure, a dynamic memory cell comprises one field effect transistor 7 and a capacitor 8. A gate electrode of the field effect transistor 7 is connected to a word line 9. A source/drain region of the field effect transistor 7 connected to the capacitor 8 is connected to a bit line 10. In data writing, a predetermined potential is applied to the word line 9. This application of the predetermined potential renders the field effect transistor 7 conductive and causes a charge applied to the bit line 10 to be stored in the capacitor 8. In data reading, a predetermined potential is applied to the word line 9. This application of the predetermined potential renders the field effect transistor 7 conductive and causes the charge stored in the capacitor 8 to be taken out through the bit line 10.
FIG. 6 is a plan view of a major portion of a conventional semiconductor memory device comprising stacked capacitor memory cells, and FIG. 7 is a sectional view taken along the line VII--VII of FIG. 6.
Referring to these figures, a field effect transistor 12 and a stacked capacitor 13 are provided on a p type semiconductor substrate 11. The field effect transistor 12 is formed in an active region 22 isolated by an oxide film 18 for isolation. The field effect transistor 12 comprises a gate electrode 15a (the word line) provided on the semiconductor substrate 11 with a gate oxide film 14, and n.sup.+ impurity regions 16a, 16b (source/drain regions) provided on a major surface of the semiconductor substrate 11. The stacked capacitor 13 comprises a storage node 19 contacting the source or drain region (the n.sup.+ impurity region 16b) of the field effect transistor 12 and extending through an interlayer insulation film 17 over the gate electrode 15a of the field effect transistor 12 and over an adjacent word line 15b, a capacitor insulation film 20 provided on the storage node 19, and a cell plate electrode 21 provided on the capacitor insulation film 20.
The semiconductor memory device structured as above, renders the source/drain region (the n.sup.+ impurity regions 16a, 16b) conductive to carry out the reading/writing operation by the selection of a word line and then the application of the predetermined potential to the gate electrode 15a.
A description will be given on a method of manufacturing the conventional semiconductor memory device comprising the above described stacked capacitor. This method is disclosed, for example, in Japanese Patent Laying-Open No. 61-183952.
Referring to FIG. 8A, a silicon oxide film 23 and a silicon nitride film 24 are formed in turn on a p.sup.+ semiconductor substrate 11 (a silicon substrate).
Referring to FIG. 8B, the silicon oxide film 23 and the silicon nitride film 24 are then patterned by photolithography so as to form an opening in a portion in which an oxide film for isolation is to be formed.
As shown in FIG. 8C, an oxide film 25 for isolation is formed on a main surface of the semiconductor substrate 11 by thermal oxidation.
Then, the silicon oxide film 23 and the silicon nitride film 24 are removed, as shown in FIGS. 8C and 8D.
Referring to FIG. 8E, a gate oxide film 14 is formed in an active region. Thereafter, a polysilicon layer 26 (which may be a doped polysilicon layer) serving as a first conductor film is formed on the overall surface of the semiconductor substrate 11 by a CVD method. A SiO.sub.2 film 27 serving as a first insulator film is then formed on the polysilicon layer 26.
Referring to FIGS. 8E and 8F, the polysilicon layer 26 and the SiO.sub.2 film 27 are then patterned in the form of the word line. Thereby, the word lines are formed. (The gate electrode 15a and the adjacent word line 15b appear in the figure).
As shown in FIGS. 8F and 8G, when phosphorus is ion-implanted, the n type impurity regions 16a, 16b located on both sides of the gate electrode 15a are formed in a self-aligned manner in the main surface of the semiconductor substrate 11. A SiO.sub.2 film 28 is then formed over the overall surface of the substrate 11 by the CVD method.
Referring to FIGS. 8G and 8H, the SiO.sub.2 film 28 is etched so that portions of the SiO.sub.2 film 28 remain on the the upper portion and the sidewall portion of the word lines (the gate electrode 15a and the adjacent word line 15b).
Then, a SiO.sub.2 film 29 serving as a second insulator film is formed on the overall surface of the semiconductor substrate 11.
Next, as shown in FIG. 8I, the SiO.sub.2 film 29 is etched so as to expose the surface of the n.sup.+ impurity region 16b formed on the main surface of the substrate 11.
Next, as shown in FIG. 8J, a polysilicon layer 30 to be a storage node is deposited on the overall surface of the semiconductor substrate 11 by the CVD method so as to contact the exposed surface of the n.sup.+ impurity region 16b.
Referring to FIG. 8K, patterning of the polysilicon layer 30 in a predetermined form results in the formation of the storage node 19.
Next, as shown in FIG. 8L, a thin film of Si.sub.3 N.sub.4 is formed on the entire surface of the substrate 11 including the storage node 19. Thereafter, an oxidation of this thin film of Si.sub.3 N.sub.4 results in formation of an oxide film 31 of Si.sub.3 N.sub.4 to be a capacitor insulation film. Then, a polysilicon film 32 (which may be a doped polysilicon film) to be a cell plate electrode is deposited on the entire surface of the substrate 11 by the CVD method.
Referring to FIGS. 8L and 8M, patterning the oxide film 31 of Si.sub.3 N.sub.4 and the polysilicon film 32 in a predetermined form causes a capacitor insulation film 20 and a cell plate electrode 21 to be formed. FIG. 8M is a sectional view corresponding to FIG. 7.
Next, as shown in FIG. 8N, an interlayer insulation film 33 (SiO.sub.2) is formed by the CVD method on the overall surface of the substrate 11 including the cell plate electrode 21. Thereafter, a contact hole 33a is formed in the interlayer insulation film 33 so as to expose the surface of the n.sup.+ impurity region 16a. Polysilicon to be a bit line is then deposited by the CVD method on the overall surface of the semiconductor substrate 11 so as to bury the contact hole 33a. Patterning this polysilicon in the form of the bit line results in formation of a bit line 34.
Since the conventional semiconductor memory device comprising the stacked capacitor is structured as above, cell capacitance is limited by an area of the planar storage node 19, as shown in FIGS. 6 and 7. Thus, the area of the storage node 19 becomes decreased with a higher degree of integration, and hence the capacitance of the memory cell becomes decreased. The amount of charges stored in the memory cell also decreases. Therefore, there are disadvantages of soft error (a phenomenon that a generation of a carrier by radiation causes a malfunction of the memory) and a degradation in an operation margin.